The HEF4520B is a dual 4-bit internally synchronous binary counter with two clock inputs (CP0 and CP1), buffered outputs from all four-bit positions (Q0 to Q3), and an asynchronous master reset input (MR). The counter advances on either the LOW-to-HIGH transition of CP0 if CP1 is HIGH or the HIGH-to-LOW transition of CP1 if CP0 is LOW. Either CP0 or CP1 may be used as the clock input to the counter and the other clock input may be used as a clock enable input. A HIGH on MR resets the counter (Q0 to Q3 = LOW) independent of CP0 and CP1. Inputs include clamp diodes. This enables the use of current-limiting resistors to interface inputs to voltages over VDD.
Features and Benefits
- Tolerant of slow clock rise and fall times
- Fully static operation
- 5 V, 10 V, and 15 V parametric ratings
- Wide supply voltage range from 3.0 V to 15.0 V
- CMOS low power dissipation
- High noise immunity
- Standardized symmetrical output characteristics
